<?xml version="1.0" encoding="utf-8"?><rss version="2.0">  <channel>    <title>Clarycon RSS feeds</title>    <link>http://www.clarycon.com</link>    <description>Clarycon&apos;s RSS news channel provides frequently updeted news on plasma technology and advanced devices.</description>    <generator>Feeder 1.0 http://reinventedsoftware.com/feeder/</generator>    <docs>http://blogs.law.harvard.edu/tech/rss</docs>    <language>en-us</language>    <pubDate>Sat, 29 Sep 2007 08:18:54 -0700</pubDate>    <lastBuildDate>Sat, 29 Sep 2007 08:18:54 -0700</lastBuildDate>    <item>      <title>Etching of porous SiOCH</title>      <link>http://www.clarycon.com/etchingofporouss.html</link>      <description><![CDATA[In this study, the effect of the mask material on the etch behavior of porous SiOCH was studied with cross section SEM, decoration methods and XPS.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 29 Sep 2007 08:18:41 -0700</pubDate>    </item>    <item>      <title>Etching of metal gates</title>      <link>http://www.clarycon.com/metalgateetch(2).html</link>      <description><![CDATA[After several years of intensive research, the IC industry is about to introduce metal gates for logic devices. New materials carry significant risks for manufacturability and reliability which seem to be justified by their benefits. Metal gates can reduce the depletion effect in p-Si, decrease the gate resistivity and minimize the dopant diffusion. For the 45 nm node and below, the industry may move from the dual doped polysilicon gates to various types of metal gate architecture. In the mid gap approach, a single metal such as TiN can be used. In the dual metal gate architecture, one n-type metal (for instance TaN) and a p-type metal (for instance WN) will be used. In the following study, we focus on the formation of TiN and TaN metal gates via substractive formation by plasma etching.<a href="http://www.clarycon.com/metalgateetch(2).html">More ...</a>]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sun, 24 Dec 2006 07:48:24 -0800</pubDate>    </item>    <item>      <title>Etching of high k dielectrics</title>      <link>http://www.clarycon.com/highketch(2).html</link>      <description><![CDATA[One of the main requirements for etching of high k dielectrics is excellent selectivity to silicon. For logic gates, this translates into the request for zero silicon recess in the source / drain area. During HfO2 deposition a thin SiO2 interfacial layer is always formed between the silicon substrate and HfO2 layer. This means that in order to achieve zero recess, one has to stop on this very thin silicon oxide interface layer. <a href="http://www.clarycon.com/highketch(2).html">More ...</a>]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 23 Dec 2006 21:28:49 -0800</pubDate>    </item>    <item>      <title>ARDE in SAC Etching</title>      <link>http://www.clarycon.com/arde_ox_pic.html</link>      <description><![CDATA[ARDE (Aspect Ratio Dependent Etching) is an effect where features with a high aspect ration (depth/width) have a higher etch rate then those with a small aspect ratio. Under certain conditions this effect can be reversed and is then called reverse ARDE. RIElag is a synonym for ARDE ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sun, 04 Jun 2006 08:39:11 -0700</pubDate>    </item>    <item>      <title>Contact Etching</title>      <link>http://www.clarycon.com/contactetch(2).html</link>      <description><![CDATA[Silicon oxides, nitrides and advanced low k materials are etched with fluorocarbon based chemistries which provide good resist selectivities. Fluorocarbon deposition plays an important role in etching of dielectrics stopping on silicon based materials like contact etching. Several studies have shown that the silicon etch rate is directly proportional to the inverse of the fluorocarbon film thickness ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sun, 07 May 2006 10:08:00 -0700</pubDate>    </item>    <item>      <title>Materials and Gas Systems in Plasma Etching</title>      <link>http://www.clarycon.com/materialsandgass.html</link>      <description><![CDATA[Slide 1: General Overview of materials and gas systems relevant for VLSI productionSlide 2: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: NiFeSlide 3: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: NiMnSbSlide 4: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: CMR materials]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:52:45 -0700</pubDate>    </item>    <item>      <title>Non-equilibrium Plasmas</title>      <link>http://www.clarycon.com/non-equilibriump.html</link>      <description><![CDATA[Plasmas used in plasma processing are non-equilibrium plasmas. Non-equilibrium plasmas are characterized by charged species with a much higher kinetic energy than neutral species.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:51:55 -0700</pubDate>    </item>    <item>      <title>Reactive and Condensable Species</title>      <link>http://www.clarycon.com/species1_pic.html</link>      <description><![CDATA[Neutral species that arrive at the wafer surface can stick to the surface and react. Depending on the sticking coefficients and reaction probabilities, reactive and condensable species can be distinguished among the species in the feed gas and the reaction products ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:51:16 -0700</pubDate>    </item>    <item>      <title>Electron Energy Distribution Function (EEDF)</title>      <link>http://www.clarycon.com/electronenergydi.html</link>      <description><![CDATA[The electron temperature of the plassma is generally lower than the threshold energies for dissociation of the feedgas molecules. Dissociation and ionization are induced by the high energy tail of the EEDF. The EEDF for inductive and capacitive plasmas are different.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:50:05 -0700</pubDate>    </item>    <item>      <title>Electron - Molecule Collisions</title>      <link>http://www.clarycon.com/electronmolecule.html</link>      <description><![CDATA[Electron Molecule Collisions are the main channel for the creation of species that are used in plasma etching: ions and radicals. Three fundamental reactions can occur when an ion strikes a molecule: electron attachment, ionization and dissociation.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:48:49 -0700</pubDate>    </item>    <item>      <title>Electron Reactions in Plasmas</title>      <link>http://www.clarycon.com/electron_reactia.html</link>      <description><![CDATA[Electron Impact Reactions convert relatively inert molecules into very reactive radicals. The role of reactive radicals is very important in plasma etching: most of the plasma surface chemistry is achieved thanks to radicals. ]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:48:04 -0700</pubDate>    </item>    <item>      <title>Surface Processes in Plasma Etching</title>      <link>http://www.clarycon.com/surface_proc_sli.html</link>      <description><![CDATA[Physical and chemical surface processes are central to plasma processing. Reactive species are created in the discharge and transported to the surface where they can react and desorp. The reation and desorption is frequently assisted by the energy of impacting ions ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:47:11 -0700</pubDate>    </item>    <item>      <title>Ions and Radicals in Plasmas</title>      <link>http://www.clarycon.com/ions_radicals_pi.html</link>      <description><![CDATA[The energy that is transferred to a plasma is ultimately stored in high energy plasma particles such as fast electrons, photons as well as atoms in high erngery states: ions and radicals ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:46:17 -0700</pubDate>    </item>    <item>      <title>Plasma Etch Mechanisms</title>      <link>http://www.clarycon.com/etch_mech_pic.html</link>      <description><![CDATA[Plasma etching is a complex process involving several elementary processes or mechanisms. Some of these processes include:- chemical etching- ion induced or enhanced etching- physical etching / ion bombardment- trenching- sidewall passivation- mask erosion]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:45:07 -0700</pubDate>    </item>    <item>      <title>Spontaneous Reactions in Plasma Etching</title>      <link>http://www.clarycon.com/spontaneousetcha.html</link>      <description><![CDATA[Chemical or so-called “spontaneous” etching is the result of the interaction of reactive free radicals with the surface. Free radicals are electrically neutral species that have incomplete outer shells such as CF3 and F ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:43:51 -0700</pubDate>    </item>    <item>      <title>The Role of Ion Bombardment in Plasma Etching</title>      <link>http://www.clarycon.com/roleofionbombara.html</link>      <description><![CDATA[When a surface is exposed to ion bombardment, atoms and molecules can be ejected ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:42:35 -0700</pubDate>    </item>    <item>      <title>Etching Profiles</title>      <link>http://www.clarycon.com/etchingprofiles(.html</link>      <description><![CDATA[In most cases, the desired etch profile is square shaped. To obtain this perfect profile, etch and passivation have to be carefully balanced and if need readjusted as the aspect ratio of the structure increase ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:41:39 -0700</pubDate>    </item>    <item>      <title>Trenching</title>      <link>http://www.clarycon.com/trenching2(plasm.html</link>      <description><![CDATA[Profile trenching is caused by ion bombardment. Ions arriving at grazing angles on the feature sidewalls get reflected and accumlulate leading to a localized higher etch rate. This effect is well known in sputter etching and in plasma processing ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:40:17 -0700</pubDate>    </item>    <item>      <title>Sidewall Passivation   </title>      <link>http://www.clarycon.com/fund_sidewall_pi.html</link>      <description><![CDATA[At room temperature etch anisotropy is always obtained thanks to the formation of a sidewall passivation layer: The sidewall passivation layer can be formed by different mechanisms ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:39:13 -0700</pubDate>    </item>    <item>      <title>Loading Effects and Aspect Ratio Dependent Etching</title>      <link>http://www.clarycon.com/microloading_pic.html</link>      <description><![CDATA[Loading effects in plasma etching can be classified into macroscopic loading, microscopic loading and etch rate depedent etching, ARDE ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:36:33 -0700</pubDate>    </item>    <item>      <title>Knudsen Transport of Neutral Species</title>      <link>http://www.clarycon.com/knudsentransport.html</link>      <description><![CDATA[RIE lag or Aspect Ratio Dependent Etching (ARDE) is particularly important for high aspect ratio etching. One of the elementary mechanisms that can contribute to ARDE is the transport mechanism of the neutrals. Plasma etching or reactive ion etching relies on the presence of reactive neutrals and ions at the etch front ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:35:12 -0700</pubDate>    </item>    <item>      <title>Charging Effects</title>      <link>http://www.clarycon.com/charging_slides.html</link>      <description><![CDATA[Charging effects during plasma etching of high aspect ratio structures can cause gate oxide degradation during gate etching and profile deformation issues such as notching or bowing. Charging effects become important for aspect ratios higher than 2:1. The origin of this phenomenon is due to the difference in directionality between ions and electrons when they cross the plasma sheath and interact with three dimensional structures ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 05 Sep 2005 08:33:51 -0700</pubDate>    </item>    <item>      <title>Temperature Effects in Plasma Etching</title>      <link>http://www.clarycon.com/temperatureeffea.html</link>      <description><![CDATA[The wafer surface temperature depends primarily on the chuck temperature, the ion density and ion energy and the exothermicity of the etching reaction ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sun, 31 Jul 2005 17:16:24 -0700</pubDate>    </item>    <item>      <title>Silicon Etching Mechanisms with HBr and Cl2</title>      <link>http://www.clarycon.com/siliconetchmecha.html</link>      <description><![CDATA[The effects of exposing a single crystalline silicon surface to a halogen plasma can be studied with spectroscopic ellipsometry (SE). The measurements show that the surface layer is partially amorphized after plasma exposure. In addition, the existance of a halogen containing layer can be shown ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sun, 31 Jul 2005 17:15:17 -0700</pubDate>    </item>    <item>      <title>Plasma and Electrode Potentials</title>      <link>http://www.clarycon.com/plasma_potentiaa.html</link>      <description><![CDATA[An RF plasma system can be represented by an equivalent circuit in the capacitive sheath approximation (slide 1). The cathode sheath and the anode (wall) sheath are represented by parallel ohmic and capacitive resistors as well as diode elements...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 16 Jul 2005 08:24:12 -0700</pubDate>    </item>    <item>      <title>Capacitive and Inductive Coupling</title>      <link>http://www.clarycon.com/plasmacoupling2.html</link>      <description><![CDATA[Most low and medium plasma density reactors utilize capacitive coupling while high density plasmas can be generated by inductively coupled, electron cyclotron resonance (ECR) and some high frequency capacitively coupled reactors.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:52:48 -0700</pubDate>    </item>    <item>      <title>MERIE and high density plasmas</title>      <link>http://www.clarycon.com/plasmadensities2.html</link>      <description><![CDATA[Slide 1 shows a comparison between low / medium and high density plasmas. Magnetically Enhanced Reactive Ion Etching (MERIE) employs a medium density plasma. Alternative ways to generate low and medium density plasmas are capacitively coupled plasma sources with relatively low exitation frequencies and powers.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:51:11 -0700</pubDate>    </item>    <item>      <title>Influence of Mask Marterials in Silicon Gate Etching</title>      <link>http://www.clarycon.com/gateetchmasks(2).html</link>      <description><![CDATA[The choice of the mask material for silicon gate etching depends on the process requirements. These materials can be grouped into carbon based materials (photoresists, bottom anireflective coatings (BARC) and carbon hardmasks) and silicon based dielectric masks (oxides, nitride, dielectric antireflective coatings (DARC)).]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:50:00 -0700</pubDate>    </item>    <item>      <title>Sidewall Passivation During Silicon Gate Etch</title>      <link>http://www.clarycon.com/sidewallpassivaa.html</link>      <description><![CDATA[During silicon gate etching, anisotropy control is obtained by the formation of a passivation layer which forms on the gate sidewall and protects it from spontaneous etching reactions. The sidewall film thickness decreases along the gate sidewall showing that profile deformation is more likely to occur at the bottom of the gate profile.]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:48:54 -0700</pubDate>    </item>    <item>      <title>The Selfclean Concept in Silicon Gate Etching.</title>      <link>http://www.clarycon.com/selfclean_pic.html</link>      <description><![CDATA[For the traditional HBr/Cl2/O2 silicon gate etch chemistry, high concentrations of etch products are present in the gas phase. These by-products can dissociate and form non volatile species ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:44:09 -0700</pubDate>    </item>    <item>      <title>RIE lag in poly-Si and silicide etching</title>      <link>http://www.clarycon.com/rielaginpoly-sia.html</link>      <description><![CDATA[RIE lag or Aspect Ratio Dependent Etching (ARDE) is particularly important for high aspect ratio gate stackes in dRAM and flash applications. The RIE lag effect can be effectively impacted by the choice of a suitable gas additive. ]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 02 May 2005 20:34:47 -0700</pubDate>    </item>    <item>      <title>Critical Dimension (CD) Control During Gate Etching</title>      <link>http://www.clarycon.com/cd_control_pic.html</link>      <description><![CDATA[The term CD control describes requirements and methods to transfer a critical dimension of a mask (for instance the length of a transistor gate) into the final dimension of the etched feature ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Mon, 13 Jun 2005 21:42:21 -0700</pubDate>    </item>    <item>      <title>Dual Gate Etching: The Doping Effect</title>      <link>http://www.clarycon.com/dualgateetchinga.html</link>      <description><![CDATA[The etch rate and profiles for n- and p-doped as well as intrinsic poly-Si can differ from each other quite significantly depending on the plasma conditions and chemistry ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 23 Apr 2005 23:02:42 -0700</pubDate>    </item>    <item>      <title>Softlanding During Gate Etching</title>      <link>http://www.clarycon.com/softlandingduria.html</link>      <description><![CDATA[As gate dielectrics are being scaled down to a few atomic layers, the plasma conditions used to form the bulk of the poly-Si gate profile can not be used anymore to land on the gate dielectric ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 23 Apr 2005 14:02:06 -0700</pubDate>    </item>    <item>      <title>Gate Oxide Integrity</title>      <link>http://www.clarycon.com/gateoxideintegra.html</link>      <description><![CDATA[Silicon to oxide etch selectivity is not the only parameter describing the thickness of the gate oxide after a gate etch process. For gate oxides with a thickness of less than 4 nm, the removal of the top oxide layer during the overetch step is accompanied by other processes which will be desccribed below ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 26 Mar 2005 15:05:28 -0800</pubDate>    </item>    <item>      <title>Shallow Trench Etch Top Corner Rounding</title>      <link>http://www.clarycon.com/shallowtrenchisc.html</link>      <description><![CDATA[The motivation for forming rounded corners at the top of the shalllow trench is based on the fact that any sharp corners result on poor gate oxide quality. The gate poly-Si can wrap around the top corner, which can create a parasitic conduction path ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 26 Mar 2005 07:12:42 -0800</pubDate>    </item>    <item>      <title>Shallow Trench Etch Bottom Corner Rounding</title>      <link>http://www.clarycon.com/shallowtrenchisa.html</link>      <description><![CDATA[The method for achieving the desired bottom corner rounding depends sginificantly on the chemistry used for shallow trench etching. Chlorine based plasmas show a tendency for microtrenching, while HBr based plasmas result more easilty in square or rounded trench bottoms ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 26 Mar 2005 07:11:20 -0800</pubDate>    </item>    <item>      <title>Fundamentals of Shallow Trench Etching</title>      <link>http://www.clarycon.com/shallowtrencheta.html</link>      <description><![CDATA[The process performance requirements for shallow trench etch are very unique and depend very much on the specifics of the device ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 26 Mar 2005 07:09:55 -0800</pubDate>    </item>    <item>      <title>Thin Gate Oxide Behavior During Overetch Step</title>      <link>http://www.clarycon.com/thingateoxidesda.html</link>      <description><![CDATA[In this study, in-situ reflectometry was used to investigate the behavior of very thin gate oxides during exposure to HBr / O2 based plasmas which are typically being used in gate overetch recipes. ]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 19 Mar 2005 22:47:53 -0800</pubDate>    </item>    <item>      <title>Resist Trimming</title>      <link>http://www.clarycon.com/resisttrim(2).html</link>      <description><![CDATA[The need for resist trimming arises from the gap between the line widths advanced lithography can print today and the desired gate length of the transistor. For the 90 nm technology node, the printed line width is typically somewhere between 90 and 100 nm and the final gate length 50 to 60 nm. Hence, a line width reduction has to be achieved at some point in the process flow, typically during the first step of the gate patterning etch ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 19 Mar 2005 19:36:28 -0800</pubDate>    </item>    <item>      <title>Design of a notched gate process</title>      <link>http://www.clarycon.com/notchedgates(2).html</link>      <description><![CDATA[Gate notching is one technique to increase transistor speed by reducing the gate length and the source drain overlay capacitance. The challenges for this technology are repeatability and measurability as well as the difficulties associated with the spacer and implant integration ...]]></description>      <author>mail@clarycon.com</author>      <pubDate>Sat, 19 Mar 2005 19:34:48 -0800</pubDate>    </item>  </channel></rss>